Menlo Park, CA, United States of America

Michael G Weaver

This inventor holds 1 USPTO granted patent. Top assignee: Synopsys, Inc.. Active years: 2008.


Average Co-Inventor Count = 5.0

ph-index = 1

Forward Citations = 7(Granted Patents)


Company Filing History:


Years Active: 2008

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1 patent (USPTO):Explore Patents

Title: Innovations by Michael G Weaver

Introduction

Michael G Weaver is an accomplished inventor based in Menlo Park, CA. He is known for his significant contributions to the field of timing analysis in circuit design. With a focus on enhancing efficiency, Weaver has developed innovative solutions that streamline complex processes.

Latest Patents

One of Weaver's notable patents is titled "Speeding up timing analysis by reusing delays computed for isomorphic subcircuits." This invention provides a system that accelerates timing analysis by reusing delays calculated for isomorphic subcircuits. The system operates by receiving a circuit block in the form of a netlist and subdividing it into a set of subcircuits. These subcircuits are then organized into equivalence classes, which consist of topologically isomorphic subcircuits. During the timing analysis, the system checks if a delay for a subcircuit has already been computed for its equivalence class. If a corresponding delay exists, it is reused; otherwise, the system computes the delay and associates it with the equivalence class for future use.

Career Highlights

Michael G Weaver is currently employed at Synopsys, Inc., where he continues to innovate in the field of electronic design automation. His work has had a profound impact on the efficiency of timing analysis, making significant strides in the industry.

Collaborations

Weaver has collaborated with notable colleagues, including Larry G Jones and Feng Li. These partnerships have contributed to the advancement of technology in their respective fields.

Conclusion

Michael G Weaver's contributions to timing analysis and circuit design exemplify the spirit of innovation. His patent on reusing delays for isomorphic subcircuits showcases his commitment to improving efficiency in electronic design.

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