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Mazhar M Alidina

This inventor holds 9 USPTO granted patents. Top assignees: Lucent Technologies Inc., Agere Systems Inc., Agere Systems Guardian Corp.. Active years: 1999-2004.

USPTO Granted Patents = 9

% Patents Active = 100.0

Average Co-Inventor Count = 2.4

ph-index = 5

Forward Citations = 525(Granted Patents)

Company Filing History:

5 out of 9,364

Lucent Technologies Inc.

Agere Systems Guardian Corp.

patents

Years Active: 1999-2004

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9 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 6819971 - Fast computation of overflow flag in a bit manipulation unit (2004-11-16),

2. 6801995 - Method for optimally encoding a set of instruction codes for a digital processor having a plurality of instruction selectable resource types and an associated optimized set of instruction codes (2004-10-05),

3. 6530014 - Near-orthogonal dual-MAC instruction set architecture with minimal encoding bits (2003-03-04),

4. 6446193 - Method and apparatus for single cycle processing of data associated with separate accumulators in a dual multiply-accumulate architecture (2002-09-03),

5. 6175912 - Accumulator read port arbitration logic (2001-01-16),

6. 6064714 - Shifter capable of split operation (2000-05-16),

7. 5991785 - Determining an extremum value and its index in an array using a (1999-11-23),

8. 5987490 - Mac processor with efficient Viterbi ACS operation and automatic (1999-11-16),

9. 5889689 - Hierarchical carry-select, three-input saturation (1999-03-30),

Title: Mazhar M Alidina: Innovator in Digital Processing Technologies

Introduction

Mazhar M Alidina is a notable inventor based in Allentown, PA (US). He has made significant contributions to the field of digital processing technologies, holding a total of 9 patents. His work focuses on enhancing the efficiency and performance of digital processors through innovative techniques.

Latest Patents

One of his latest patents is titled "Fast computation of overflow flag in a bit manipulation unit." This invention involves a bit manipulation unit (BMU) that scales and formats data while enabling the fast computation of the overflow flag. The overflow flag is computed based on the input data and the shift amount, allowing for parallel processing with the barrel shift operation. This technique significantly reduces the time required for a BMU to calculate the overflow flag.

Another notable patent is the "Method for optimally encoding a set of instruction codes for a digital processor having a plurality of instruction selectable resource types and an associated optimized set of instruction codes." This method assigns unique instruction codes to instructions in an instruction set, grouping them according to the resources used. By optimizing the encoding scheme, it eliminates wasted bits in instructions, thereby increasing the number of instructions that can be implemented.

Career Highlights

Mazhar has worked with prominent companies in the technology sector, including Lucent Technologies Inc. and Agere Systems Inc. His experience in these organizations has contributed to his expertise in digital processing and innovation.

Collaborations

Throughout his career, Mazhar has collaborated with talented individuals such as Sivanand Simanapalli and Larry R Tate. These collaborations have further enriched his work and contributed to the development of advanced technologies.

Conclusion

Mazhar M Alidina is a distinguished inventor whose work in digital processing technologies has led to significant advancements in the field. His innovative patents and contributions continue to influence the industry and inspire future developments.

Profile summary based on public USPTO records.

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