Lucent Technologies Inc.

Agere Systems Inc.

Agere Systems Guardian Corp.

Mazhar M Alidina

Sivanand Simanapalli

Larry R Tate

Mark Ernest Thierbach

Alexander Goldovsky

Geoffrey Francis Burns

Bin Fu

A bit manipulation unit (BMU) scales and formats data and includes fast computation of the overflow flag. For fast computation the BMU's overflow flag is computed based on the input data and the shift amount. The overflow flag is calculated separately as either a LMV for an arithmetic shift left operation or LMV for an arithmetic shift right operation. For an arithmetic shift left operation, LMV may be computed by first adding one plus the number of guard bits in the input data to the shift amount, and then detecting the number of redundant sign bits. For an arithmetic shift right operation, LMV may be computed by checking the input redundant sign bits plus the right shift amount. By computing the overflow flag separately as LMV and LMV for arithmetic left and right shifts, respectively, the overflow flag LMV is determined in parallel with the barrel shift operation and so does not depend on the result from the barrel shift operation. Consequently, an advantage of employing this technique in a BMU may be a relative reduction in the time necessary for a BMU to calculate the overflow flag.

Fast computation of overflow flag in a bit manipulation unit

A method of assigning unique instruction codes to instructions in an instruction set is disclosed. Such an encoded instruction set is also disclosed. Instructions are grouped according to the particular resources used, where all of the instructions in a group have one or more resource types in common. The position of the highest order active bit in the code is used to identify which resource group a particular instruction belongs to. Instructions in a resource group reserve the same number of bits to identify the specific resources to be used, and no more bits are reserved than required. The remaining unassigned bits are used to encode particular command codes. When such an encoded command is decoded, the resource group is identified by determining the highest order active bit in the instruction. This information is used to determine which bits in the instruction are command bits and which are resource-identifying bits. The specific resource information is extracted and used to select the designated resources to be used in executing the command. This encoding scheme eliminates wasted bits in instructions and thereby increases the number of instructions which can be implemented.

Method for optimally encoding a set of instruction codes for a digital processor having a plurality of instruction selectable resource types and an associated optimized set of instruction codes

A near-orthogonal dual-MAC instruction set is provided which implements virtually the entire functionality of the orthogonal instruction set of 272 commands using only 65 commands. The reduced instruction set is achieved by eliminating instructions based on symmetry with respect to the result of the commands and by imposing simple restrictions related to items such as the order of data presentation by the programmer. Specific selections of commands are also determined by the double word aligned memory architecture which is associated with the dual-MAC architecture. The reduced instruction set architecture preserves the functionality and inherent parallelism of the command set and requires fewer command bits to implement than the full orthogonal set.

Near-orthogonal dual-MAC instruction set architecture with minimal encoding bits

A method and apparatus for reducing instruction cycles in a digital signal processor wherein the processor includes a multiplier unit, an adder, a memory, and at least one pair of first and second accumulators. The accumulators include respective guard, high and low parts. The method and apparatus enable vectoring the respective first and second high parts from the accumulators to define a single vectored register responsive to a single instruction cycle and processing the data in the vectored register.

Method and apparatus for single cycle processing of data associated with separate accumulators in a dual multiply-accumulate architecture

A processor architecture having an accumulator register file with multiple shared read and/or write ports. Depending on the instruction, each port can be used to communicate with a different data source or destination.

Accumulator read port arbitration logic

A device for shifting data in a cascade multiplexer shifter allows the shifter to be used in a full-length mode or in a split mode where the shifter is divided into two equal halves with upper and lower half fields thereof respectively receiving individual data numbers. Each data number is thereafter simultaneously shifted right or shifted left a given shift amount to effect a dual right or dual left shift function.

Shifter capable of split operation

A data processor determines an overall extremum value of an input set of array data, with the input set of array data partitionable into a first set of array data and a second set of array data. The data processor includes a pair of compare-select circuits implemented in an adder as well as in an arithmetic-logic unit (ALU), respectively, which operate in parallel for respectively processing the first set and the second set, and for respectively determining first and second extremum values of the first set and the second set, respectively. A first compare-select circuit of the pair of compare-select circuits determines the overall extremum value of the input set of array data from the first and second extremum values. The first compare-select circuit also determines the location of the overall extremum value in the input set of array data. The computational complexity in determining extrema is reduced by implementing compare-select features in an adder in addition to an ALU to operate in parallel to reduce the number of processing cycles.

Determining an extremum value and its index in an array using a

A dual-MAC processor optimized so that two Viterbi ACS operations, including traceback bit storage, can be executed in two machine cycles is disclosed. The processor comprises a pair of adder arithmetic logic units connected to a common accumulator register bank and supporting full and split-mode add, subtract, and compare operations. Viterbi compare operations are executed using the subtract function and the sign bit is combined with a compare mode bit to generate a traceback output which indicates the proper traceback bit to store. When a compare operation is performed and a Viterbi mode bit is active, each generated traceback output is shifted into a traceback register for later use in a Viterbi traceback routine.

Mac processor with efficient Viterbi ACS operation and automatic

There is disclosed a first adder subtractor combines the largest positive number or largest negative number capable of being represented by the number of bits in the datapath, as determined by the sign of an input to a second adder with a first input to generate a first potential sum. A second adder operating in parallel with the first adder combines first, second and third inputs to generate a second potential sum. An overflow detector combines the first and second inputs of the second adder to determine if there is an overflow. If an overflow is not present, a multiplexer selects the output of the second adder as the output to be saturated. If an overflow is present, the multiplexer selects the output from the first adder as the output to be saturated.

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Allentown, PA, United States of America

Mazhar M Alidina