Dallas, TX, United States of America

Masoud Farhadi

This inventor holds 2 USPTO granted patents. Top assignee: The University of Texas System. Active years: 2023-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Masoud Farhadi. Retrieved from https://idiyas.com/inventor/masoud-farhadi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 50.0

Average Co-Inventor Count = 5.0

ph-index = 1


Company Filing History:


Years Active: 2023-2026

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2 patents (USPTO):Explore Patents

Title: Masoud Farhadi: Innovator in MOS Technology

Introduction

Masoud Farhadi is a notable inventor based in Dallas, TX, specializing in advancements in MOS technology. He has made significant contributions to the field through his innovative patent, which addresses critical issues in insulated gate transistors.

Latest Patents

Farhadi holds a patent titled "Systems, circuits, and methods to detect gate-open failures in MOS based insulated gate transistors." This invention provides a comprehensive system designed to detect gate-open failures in MOS-based insulated gate transistors. The system includes a detection circuit that measures the drain-source voltage across the transistor and employs comparator circuits to assess the conduction state of the channel. Additionally, it features a logic circuit that identifies gate-open failures based on the conduction state and gate voltage sufficiency.

Career Highlights

Masoud Farhadi is affiliated with the University of Texas System, where he continues to contribute to research and development in semiconductor technology. His work has implications for improving the reliability and efficiency of electronic devices that utilize MOS technology.

Collaborations

Farhadi has collaborated with talented individuals such as Bhanu Teja Vankayalapati and Bilal Akin, enhancing the scope and impact of his research.

Conclusion

Masoud Farhadi's innovative work in detecting gate-open failures in MOS technology showcases his commitment to advancing the field of electronics. His contributions are vital for the development of more reliable and efficient electronic systems.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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