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For the Inventor, By the Inventor

Kawasaki, Japan

Masashi Arayama

This inventor holds 6 USPTO granted patents and 5 published patent applications. Top assignee: Fujitsu Corporation. Active years: 2002-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Masashi Arayama. Retrieved from https://idiyas.com/inventor/masashi-arayama

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 6 

% Patents Active = 33.3

Average Co-Inventor Count = 1.6

ph-index = 3

Forward Citations = 12(Granted Patents)


Location History:

  • Yokohama, JP (2002)
  • Kawasaki, JP (2010 - 2013)
  • Gamagori, JP (2014)

Company Filing History:

goldMedal6 out of 39,371 
 
Fujitsu Corporation
 patents

Years Active: 2002-2014

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6 patents (USPTO):Explore Patents
1. 8689167 - Layout design apparatus and layout design method (2014-04-01),
2. 8539412 - Macro layout verification appartus (2013-09-17),
3. 8286117 - Macro layout verification apparatus to detect error when connecting macro terminal in LSI design layout (2012-10-09),
4. 8000951 - Timing analysis method and apparatus for enhancing accuracy of timing analysis and improving work efficiency thereof (2011-08-16),
5. 7739638 - Circuit analyzing device, circuit analyzing method, program, and computer readable information recording medium considering influence of signal input to peripheral circuit which does not have logical influence (2010-06-15),
6. 6434728 - Activation path simulation equipment and activation path simulation method (2002-08-13),

Title: Masashi Arayama: Innovator in Layout Design Technology

Introduction

Masashi Arayama is a prominent inventor based in Kawasaki, Japan. He has made significant contributions to the field of layout design technology, particularly in the context of multilayer circuits. With a total of 6 patents to his name, Arayama's work has had a substantial impact on the semiconductor industry.

Latest Patents

Arayama's latest patents include a layout design apparatus and a macro layout verification apparatus. The layout design apparatus features a memory unit that stores design data of a hierarchical layout of a multilayer circuit, including a macro. It also includes a channel count calculation unit that calculates the available channels for wiring from a terminal of the macro to a wiring layer. Additionally, a path calculation unit is incorporated to determine the optimal path for leading wiring based on the calculated channel count. The macro layout verification apparatus is designed to verify the layout of a macro intended for placement as a functional block on a semiconductor device. This apparatus includes a unit that assumes a virtual wiring line using an unused intra-macro channel and calculates the parallel wiring length, outputting information when this length exceeds a defined reference value.

Career Highlights

Masashi Arayama is currently employed at Fujitsu Corporation, where he continues to innovate and develop advanced technologies in layout design. His expertise and contributions have positioned him as a key figure in his field.

Collaborations

Throughout his career, Arayama has collaborated with notable colleagues, including Sumiko Makino and Eiji Furuta. These collaborations have further enhanced the quality and impact of his work.

Conclusion

Masashi Arayama's innovative contributions to layout design technology have established him as a leading inventor in the semiconductor industry. His patents reflect a commitment to advancing technology and improving design methodologies.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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