The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8689167 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 01, 2014

Filed:

Jun. 27, 2012
Applicants:

Masashi Arayama, Gamagori, JP;

Yuuki Watanabe, Toyohashi, JP;

Inventors:

Masashi Arayama, Gamagori, JP;

Yuuki Watanabe, Toyohashi, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A layout design apparatus includes: a memory unit to store design data of a hierarchical layout of a multilayer circuit including a macro; a channel count calculation unit to calculate a channel count of channels available to lead wiring from a terminal of the macro to a wiring layer based on the design data stored in the memory unit; and a path calculation unit to calculate a path for leading wiring from a terminal of the macro to the wiring layer in ascending order of the channel count.


Find Patent Forward Citations

Arayama, Masashi. (2014). Layout design apparatus and layout design method (U.S. Patent No. 8689167). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8689167

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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