La Cañada Flintridge, CA, United States of America

Mark Hatzilambrou

This inventor holds 2 USPTO granted patents. Top assignee: Institute of Microelectronics. Active years: 2003-2004.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Mark Hatzilambrou. Retrieved from https://idiyas.com/inventor/mark-hatzilambrou

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 6.0

ph-index = 2

Forward Citations = 82(Granted Patents)


Location History:

  • Singapore, SG (2003)
  • La Canada, CA (US) (2004)

Company Filing History:


Years Active: 2003-2004

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2 patents (USPTO):Explore Patents

Title: **Mark Hatzilambrou: Innovator in Electrostatic Discharge Protection and RF IC Integration**

Introduction

Mark Hatzilambrou is a distinguished inventor based in La Canada, California, recognized for his contributions to the fields of electrostatic discharge (ESD) protection systems and integrated circuit component integration. With two patents to his name, Hatzilambrou has made significant strides in advancing technology that addresses critical challenges in high-frequency applications and copper interconnect processes.

Latest Patents

Mark Hatzilambrou's latest patents showcase his innovative thinking and advanced technical expertise. His first patent details an **ESD protection system for high-frequency applications**. This system offers electrostatic discharge protection for circuits utilizing multiple power supply rails, ensuring that Vdd busses remain isolated while Vss busses are interconnected through pairs of complementary polarity diodes. The design of the I/O diodes within high-frequency I/O pads is arranged in a square layout to optimize current/capacitance ratios, while each pair of power rails is equipped with a dedicated power shunt circuit designed to activate at low voltage levels during ESD events.

His second patent introduces a **single damascene method for RF IC passive component integration in copper interconnect process**. This method emphasizes efficiently integrating various components, such as spiral inductors, MIM capacitors, and precision resistors, within a planar copper interconnect configuration. By meticulously layering these components, Hatzilambrou's approach enhances the performance and reliability of integrated circuits.

Career Highlights

Mark Hatzilambrou has established himself as a valuable figure within the Institute of Microelectronics, where he has been instrumental in pioneering innovative solutions that meet the demands of modern technology. His work reflects a commitment to developing systems that not only enhance performance but also improve the safeguarding of sensitive electronics against potential damage.

Collaborations

Throughout his career, Hatzilambrou has collaborated with talented individuals like Chester Leung and Eric Johnson. These partnerships emphasize the power of teamwork in the pursuit of technological advancements, enabling him to harness diverse perspectives and expertise to achieve common goals.

Conclusion

Mark Hatzilambrou’s contributions are a testament to the impact of innovation in the technology sector. By focusing on critical areas such as ESD protection and integrated circuit design, he has helped shape the future of electronic applications. As technology continues to evolve, Hatzilambrou's work will undoubtedly continue to influence the landscape of electronics engineering and innovation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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