The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 2004
Filed:
Aug. 23, 2001
Mark Hatzilambrou, La Canada, CA (US);
Chester Leung, Northfield, GB;
Rajan Walia, Singapore, SG;
Lien Wee Liang, Singapore, SG;
Subhash C. Rustagi, Singapore, SG;
M K Radhakrishnan, Singapore, SG;
Institute of Microelectronics, Singapore, SG;
Abstract
Electrostatic discharge (ESD) protection for circuits which utilize multiple power supply rails, both positive (Vdd) and negative (Vss). Vdd busses remain completely isolated, while Vss busses are joined by pairs of complementary polarity diodes (made typically with P+/N-well diodes in an N/P-substrate process) thus keeping Vss busses isolated from each other. The I/O diodes of high frequency I/O pads are arranged in a square layout to achieve the best current/capacitance ratio. Each pair of power rails is provided with its own power shunt circuit, placing each shunt in physical proximity to the I/O pad it must protect. Shunts are designed to clamp at a very low voltage during an ESD event using mostly PMOS transistors. The protection circuit is laid out such that the worst case ESD event will flow at most between two I/O pads and one power shunt.