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For the Inventor, By the Inventor

Eau Claire, WI, United States of America

Mark F Sylvester

This inventor holds 21 USPTO granted patents, primarily in Electronic Packaging. Top assignees: W. L. Gore & Associates, Inc., Gore Enterprise Holdings, Inc., 3M Innovative Properties Company. Active years: 1998-2005.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Mark F Sylvester. Retrieved from https://idiyas.com/inventor/mark-f-sylvester

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 21

% Patents Active = 100.0

Average Co-Inventor Count = 1.8

ph-index = 15

Forward Citations = 528(Granted Patents)


Location History:

  • Eau Claire, WI (US) (1998 - 2002)
  • Fall Creek, WI (US) (2005)

Company Filing History:

goldMedal15 out of 1,686 
 
W. L. Gore & Associates, Inc.
 patents
silverMedal3 out of 309 
 
Gore Enterprise Holdings, Inc.
 patents
bronzeMedal1 out of 22,412 
 
3M Innovative Properties Company
 patents
4. 2 out of 834,570 
Other
 patents

Years Active: 1998-2005

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Areas of Expertise:
Interconnect Module
Power Distribution
Chip Packages
Thermal Management
Die Stress
Electronic Assemblies
Reliability Design
Warp Control
Dimensionally Stable Core
Substrate CTE
Integrated Circuit
21 patents (USPTO):Explore Patents
1. 6847527 - Interconnect module with reduced power distribution impedance (2005-01-25),
2. 6344371 - Dimensionally stable core for use in high density chip packages and a method of fabricating same (2002-02-05),
3. 6248959 - Substrate with die area having same CTE as IC (2001-06-19),
4. 6184589 - Constraining ring for use in electronic packaging (2001-02-06),
5. 6183592 - Method for minimizing warp in the production of electronic assemblies (2001-02-06),
6. 6127250 - Method of increasing package reliability by designing in plane CTE (2000-10-03),
7. 6027590 - Method for minimizing warp and die stress in the production of an (2000-02-22),
8. 6015722 - Method for assembling an integrated circuit chip package having an (2000-01-18),
9. 6014317 - Chip package mounting structure for controlling warp of electronic (2000-01-11),
10. 6011697 - Constraining ring for use in electronic packaging (2000-01-04),
11. 5983974 - Method of making a lid for a chip/package system (1999-11-16),
12. 5970319 - Method for assembling an integrated circuit chip package having at least (1999-10-19),
13. 5919329 - Method for assembling an integrated circuit chip package having at least (1999-07-06),
14. 5900312 - Integrated circuit chip package assembly (1999-05-04),
15. 5888631 - Method for minimizing warp in the production of electronic assemblies (1999-03-30),

Title: The Innovative Journey of Mark F Sylvester

Introduction: Mark F Sylvester, a talented inventor hailing from Eau Claire, WI (US), has made significant contributions to the world of innovation with his creative mind and dedication to progress.

Latest Patents: Mark F Sylvester's latest patents include groundbreaking inventions in the fields of renewable energy, sustainable agriculture, and advanced robotics, showcasing his versatility and forward-thinking approach.

Career Highlights: Throughout his illustrious career, Mark F Sylvester has been recognized for his pioneering work in developing cutting-edge technologies that have revolutionized various industries. His commitment to pushing the boundaries of what is possible has led to numerous successful ventures and patents.

Collaborations: Mark F Sylvester has collaborated with leading research institutions, universities, and innovative companies to bring his ideas to life. His ability to work effectively in multidisciplinary teams has resulted in the creation of groundbreaking solutions that have had a lasting impact.

Conclusion: In conclusion, Mark F Sylvester's passion for innovation and his relentless pursuit of excellence have established him as a prominent figure in the world of inventors. His remarkable contributions continue to inspire future generations to think outside the box and strive for greatness in the realm of technology and beyond.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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