Sunnyvale, CA, United States of America

Manjunath D Haritsa

This inventor holds 3 USPTO granted patents and 2 published patent applications. Top assignee: Sun Microsystems, Inc.. Active years: 2003-2005.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Manjunath D Haritsa. Retrieved from https://idiyas.com/inventor/manjunath-d-haritsa

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 3 

% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 3

Forward Citations = 81(Granted Patents)


Location History:

  • San Jose, CA (US) (2003)
  • Sunnyvale, CA (US) (2005)

Company Filing History:


Years Active: 2003-2005

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3 patents (USPTO):Explore Patents

Title: Manjunath D Haritsa: Innovator in Microprocessor Design

Introduction

Manjunath D Haritsa is a prominent inventor based in Sunnyvale, CA. He has made significant contributions to the field of microprocessor design, holding a total of 3 patents. His innovative methodologies have advanced the way clock distribution and noise estimation are handled in integrated circuits.

Latest Patents

One of his latest patents is titled "Clock skew verification methodology for grid-based design." This invention provides a method and apparatus for determining clock insertion delays in microprocessor designs that utilize a grid-based clock distribution. The process involves partitioning the complete clock net into a global clock net and several local clock nets. It includes simulating loads for each local clock net, simulating the global clock net, and combining these simulations to form the complete clock net. The method evaluates the combination to check for convergence and stores the results in a Clock Data Model. If the results do not converge, the method re-simulates the local and global clock nets. The Clock Data Model is essential for managing and querying all simulation information, and it can analyze the complete clock net to predict clock skew for potential redesigns.

Another notable patent is the "System and method for topology based noise estimation of submicron integrated circuit designs." This tool computes noise coupled onto victim lines from aggressor lines within an integrated circuit. It includes code for traversing a victim line to measure its length, average width, coupling length, and spacing between the victim and aggressor lines. The tool computes resistance, estimated coupling capacitance, and total capacitance of the victim line based on these parameters.

Career Highlights

Manjunath D Haritsa is currently employed at Sun Microsystems, Inc., where he continues to innovate in the field of microprocessor design. His work has had a lasting impact on the industry, particularly in improving the reliability and efficiency of integrated circuits.

Collaborations

He has collaborated with notable colleagues such as Stephan Hoerold and Kathirqamar Aingaran, contributing to various projects that enhance the capabilities of microprocessor technology.

Conclusion

Manjunath D Haritsa is a distinguished inventor whose work in microprocessor design has led to significant advancements in the field. His patents reflect a deep understanding of clock distribution and noise estimation, making him a valuable asset to the technology industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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