Manish Baronia

Title: Manish Baronia: Innovator in Integrated Circuit Design

Introduction

Manish Baronia is a notable inventor based in Gargaon, India. He has made significant contributions to the field of integrated circuit design, particularly in achieving clock timing closure. His innovative approach has led to advancements that enhance the efficiency and reliability of integrated circuits.

Latest Patents

Manish Baronia holds a patent titled "Achieving clock timing closure in designing an integrated circuit." This patent involves virtually synthesizing a clock network for integrated circuit design to generate virtual clock buffering before the clock network is synthesized and committed to a netlist. The process includes determining timing violations for clock gates generated by the virtual clock buffering. Clock gating transforms are evaluated based on recalculated clock and data path delays to incrementally synthesize the clock network. The most effective clock gating transforms are then committed to the netlist, leading to an optimized clock network synthesis for the integrated circuit design.

Career Highlights

Manish Baronia is currently employed at Cadence Design Systems, Inc., where he continues to innovate in the field of integrated circuit design. His work focuses on improving design methodologies and enhancing the performance of electronic systems.

Collaborations

One of his notable coworkers is Sourav Kumar Sircar, with whom he collaborates on various projects within the company.

Conclusion

Manish Baronia's contributions to integrated circuit design through his patent and work at Cadence Design Systems, Inc. highlight his role as an influential inventor in the technology sector. His innovative methods are paving the way for advancements in electronic design.