Sagamihara, Japan

Manami Mizukane

This inventor holds 1 USPTO granted patent. Top assignee: Micron Technology Incorporated. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Manami Mizukane. Retrieved from https://idiyas.com/inventor/manami-mizukane

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Manami Mizukane: Semiconductor Memory Design Inventor.

Introduction

Manami Mizukane is an inventor associated with Sagamihara, Japan, and Micron Technology Incorporated. Her patent work concerns semiconductor memory architecture and circuitry for controlling access to memory cells.

Latest Patents

Mizukane is named on one patent, Semiconductor Device Having Row Decoder Circuit. The invention describes first and second memory cell arrays, with sub word line drivers, main word line drivers, and level shift circuits arranged in an intermediate region between the arrays. The level shift circuits provide voltage-level-shifted signals to the main word line drivers, supporting the row-decoder circuitry.

Career Highlights

Mizukane’s listed patent portfolio comprises 1 patent. Her work reflects a focus on semiconductor devices and the circuitry used to operate memory arrays.

Collaborations

Katsunari Murayama and Mamoru Nishizaki are identified as Mizukane’s coworkers. The available information does not specify their roles in the patent.

Conclusion

Manami Mizukane’s patent on a semiconductor device with a row decoder circuit highlights her contribution to memory-device design at Micron Technology Incorporated.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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