Manabu Yamazaki

Title: Manabu Yamazaki and His Semiconductor Deposition Patents.

Introduction

Manabu Yamazaki is an inventor based in Chiba, Japan, whose patent work concerns tungsten deposition processes used in semiconductor manufacturing. His listed portfolio includes 2 patents, and he works at Applied Materials, Inc.

Latest Patents

Yamazaki’s listed patents address chemical vapor deposition (CVD) of tungsten and control of film formation on semiconductor wafers.

“Chemical Vapor Deposition Process for Depositing Tungsten” describes a multistep process for depositing tungsten on a substrate. It begins with a nucleation step using tungsten hexafluoride (WF₆) and silane (SiH₄). After those gases are stopped, diborane is introduced for 5 to 25 seconds. The bulk deposition step then resumes the WF₆ flow alongside hydrogen and diborane; a preferred embodiment also introduces nitrogen.

“Suppression of Tungsten Film Deposition on a Semiconductor Wafer Bevel” describes a CVD method and apparatus designed to limit tungsten film formation at a wafer’s peripheral edge. A halogenide purge gas is supplied to that region during deposition, where it interacts with process gases to form a passivation film. The approach is intended to reduce edge buildup and particles during chemical-mechanical polishing, supporting cleaner wafers and reliable multilayer electrode wiring.

Career Highlights

At Applied Materials, Yamazaki’s work, as reflected in these patents, focuses on improving tungsten deposition and managing film formation across semiconductor wafer surfaces. The described techniques address process control, wafer-edge protection, and manufacturing quality.

Collaborations

Yamazaki’s listed coworkers include Yuji Maeda and Keiichi Ohtsuka. Their inclusion identifies professional connections associated with his work, though the supplied information does not specify their roles in the patents.

Conclusion

Manabu Yamazaki’s two listed patents focus on controlled tungsten deposition and suppression of unwanted film formation at wafer edges, addressing practical challenges in semiconductor manufacturing.