The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 1999

Filed:

Jul. 14, 1997
Applicant:
Inventors:

Yuji Maeda, Chiba, JP;

Katsumi Mitani, Chiba, JP;

Manabu Yamazaki, Chiba, JP;

Naomi Yoshida, Chiba, JP;

Keiichi Tanaka, Chiba, JP;

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438680 ; 118728 ;
Abstract

Provided herein is a CVD method and apparatus for the deposition of tungsten in which formation of a film of tungsten material is suppressed at the peripheral edge of the semiconductor substrate. In accordance with the invention, a halogenide purge gas is supplied to the peripheral edge of the processing face of a semiconductor wafer during the chemical vapor deposition of tungsten. The halogenide purge gases interact with the processing gases and form a passivation film at the peripheral edge of the semiconductor wafer which suppresses or prevents the formation of a film of tungsten material on the edge surface. Consequently, CMP can be applied to the tungsten semiconductor wafer, and particles of the tungsten material, etc., are not generated from the intense polishing of the peripheral edge of the wafer. Therefore, an uncontaminated tungsten-coated semiconductor wafer with a precise multilayer electrode wiring structure can be manufactured in large volume and favorable yields.


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