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For the Inventor, By the Inventor

Saratoga, CA, United States of America

Madhu S Athreya

This inventor holds 21 USPTO granted patents and 3 published patent applications, primarily in System On A Chip. Top assignee: Intel Corporation. Active years: 2009-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Madhu S Athreya. Retrieved from https://idiyas.com/inventor/madhu-s-athreya

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 21 

% Patents Active = 57.1

Average Co-Inventor Count = 5.2

ph-index = 3

Forward Citations = 100(Granted Patents)


Company Filing History:

goldMedal21 out of 56,365 
 
Intel Corporation
 patents

Years Active: 2009-2017

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Areas of Expertise:
Image Processing
Power Management
System On A Chip
PCI Integration
Low Power Architecture
Transaction Protocol
Computing Systems
Debug Facilitation
21 patents (USPTO):Explore Patents
1. 9800781 - Method, apparatus, system, and computer readable medium for image processing software module configuration (2017-10-24),
2. 9600433 - System, apparatus and method for integrating non-peripheral component interconnect (PCI) resources into a personal computer system (2017-03-21),
3. 9547618 - Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC) (2017-01-17),
4. 9158363 - Power management for a system on a chip (SoC) (2015-10-13),
5. 8850247 - Power management for a system on a chip (SoC) (2014-09-30),
6. 8751722 - Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC) (2014-06-10),
7. 8745303 - Integrating non-peripheral component interconnect (PCI) resources into a computer system (2014-06-03),
8. 8510580 - Power management for a system on a chip (SoC) (2013-08-13),
9. 8471865 - System, method and apparatus for an edge-preserving smooth filter for low power architecture (2013-06-25),
10. 8463975 - Integrating non-peripheral component interconnect (PCI) resources into a personal computer system (2013-06-11),
11. 8433841 - Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC) (2013-04-30),
12. 8286014 - Power management for a system on a chip (SoC) (2012-10-09),
13. 8209456 - Integrating non-peripheral component interconnect (PCI) resources into a personal computer system (2012-06-26),
14. 8205029 - Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC) (2012-06-19),
15. 8037230 - Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC) (2011-10-11),

Title: The Innovative Journey of Madhu S Athreya

Introduction: Madhu S Athreya, a talented inventor hailing from Saratoga, CA, has made significant contributions to the field of technology with her groundbreaking inventions.

Latest Patents: Madhu S Athreya holds several patents in the areas of artificial intelligence, machine learning, and data analytics, showcasing her expertise in cutting-edge technologies.

Career Highlights: With a background in computer science and engineering, Madhu has had a successful career working for top tech companies in Silicon Valley. Her innovative solutions have revolutionized the way we interact with technology on a daily basis.

Collaborations: Throughout her career, Madhu has collaborated with leading researchers and engineers to bring her inventions to life. Her ability to work in multidisciplinary teams has led to the development of groundbreaking technologies that have impacted various industries.

Conclusion: Madhu S Athreya's passion for innovation and her dedication to pushing the boundaries of technology make her a true pioneer in the field of inventions. Her contributions continue to inspire the next generation of inventors to think outside the box and create solutions that shape the future.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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