Mountain View, CA, United States of America

Luc Francois Vidal

This inventor holds 1 USPTO granted patent. Top assignee: Synopsys, Inc.. Active years: 2023.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Luc Francois Vidal. Retrieved from https://idiyas.com/inventor/luc-francois-vidal

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 6.0

ph-index = 1


Company Filing History:


Years Active: 2023

Loading Chart...
1 patent (USPTO):Explore Patents

Title: Luc Francois Vidal: Innovator in Circuit Design Verification

Introduction

Luc Francois Vidal is a notable inventor based in Mountain View, CA (US). He has made significant contributions to the field of circuit design verification, particularly through his innovative patent.

Latest Patents

Vidal holds a patent for a "High speed, low hardware footprint waveform." This invention describes a method of capturing signals during hardware verification of a circuit design. It utilizes at least one field-programmable gate array (FPGA) and involves selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification. The values of these signals are stored in at least first and second random access memories within the FPGA. Notably, the first and second random access memories may be addressable spaces of the same random access memory. He has 1 patent to his name.

Career Highlights

Vidal is currently employed at Synopsys, Inc., where he continues to develop and refine technologies related to circuit design. His work has been instrumental in advancing the efficiency and effectiveness of hardware verification processes.

Collaborations

Some of his notable coworkers include Arturo Salz and Ching-Ping Chou, who contribute to the innovative environment at Synopsys, Inc.

Conclusion

Luc Francois Vidal is a prominent figure in the realm of circuit design verification, with a focus on enhancing hardware verification methods. His contributions are paving the way for future advancements in the field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…