Shanghai, China

Louis Liu

This inventor holds 1 USPTO granted patent. Top assignee: Cadence Design Systems, Inc.. Active years: 2010.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Louis Liu. Retrieved from https://idiyas.com/inventor/louis-liu-15ysrvg4

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 5.0

ph-index = 1

Forward Citations = 3(Granted Patents)


Company Filing History:


Years Active: 2010

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1 patent (USPTO):Explore Patents

Title: Louis Liu - Innovator in Design for Testing

Introduction

Louis Liu is a prominent inventor based in Shanghai, China. He has made significant contributions to the field of design for testing (DFT) through his innovative approaches. His work focuses on improving the efficiency of design processes in the technology sector.

Latest Patents

Louis Liu holds a patent for "Performing early DFT-aware prototyping of a design." This invention relates to conducting early design for testing-aware prototyping. Unlike prior approaches, his method analyzes and considers the impact of test structures at a very early stage of the design process. This improvement allows for a more efficient iterative and incremental consideration of test structures, ultimately reducing design cycle time and costs. He has 1 patent to his name.

Career Highlights

Louis Liu is currently employed at Cadence Design Systems, Inc., a leading company in electronic design automation. His role involves leveraging his expertise to enhance design methodologies and contribute to innovative solutions in the industry.

Collaborations

Throughout his career, Louis has collaborated with notable professionals, including Kit Lam Cheong and Ping-Chih Wu. These collaborations have further enriched his work and contributed to advancements in design for testing.

Conclusion

Louis Liu is a key figure in the realm of design for testing, with a focus on early prototyping methods that enhance efficiency and reduce costs. His contributions continue to shape the future of design processes in technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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