Taipei, Taiwan

Li-Ta Chen

This inventor holds 1 USPTO granted patent. Top assignee: Powerchip Semiconductor Manufacturing Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Li-Ta Chen. Retrieved from https://idiyas.com/inventor/li-ta-chen

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Li-Ta Chen and Semiconductor Patterning Innovation.

Introduction

Li-Ta Chen is an inventor based in Taipei, Taiwan, associated with Powerchip Semiconductor Manufacturing Corporation. Chen’s patent work addresses semiconductor manufacturing, particularly the formation of select gates and word lines through double patterning.

Latest Patents

Chen is credited with 1 patent: “Double Patterning Method of Manufacturing Select Gates and Word Lines.” The invention forms first string patterns on a target layer, adds a conformal spacer layer, and fills the resulting trenches to create spaced second string patterns. The patterns are then used as a mask during etching to form word lines and select gates.

Career Highlights

Chen’s documented patent contribution focuses on a method for producing semiconductor features through a sequence of pattern formation, trench filling, spacer removal, and etching. This approach is intended to create the target patterns needed to manufacture select gates and word lines.

Collaborations

Chen is associated with Powerchip Semiconductor Manufacturing Corporation. The provided information also identifies Yi-Yeh Chuang and Zih-Song Wang as coworkers.

Conclusion

Li-Ta Chen’s patent reflects a contribution to semiconductor fabrication, using double patterning to form select gates and word lines on a target layer.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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