Chapel Hill, NC, United States of America

Lee Mc Carthy

This inventor holds 1 USPTO granted patent. Top assignee: Other. Active years: 2003.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Lee Mc Carthy. Retrieved from https://idiyas.com/inventor/lee-mc-carthy

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 236(Granted Patents)


Company Filing History:

goldMedal1 out of 834,601 
Other
 patents

Years Active: 2003

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1 patent (USPTO):Explore Patents

Title: Lee Mc Carthy and His Work on Group III Nitride Transistors.

Introduction

Lee Mc Carthy is an inventor associated with Chapel Hill, North Carolina. His patent work addresses ways to improve the high-frequency performance of Group III nitride field-effect transistors and high electron mobility transistors.

Latest Patents

The available information lists 1 patent for Mc Carthy: “Group III nitride based FETs and HEMTs with reduced trapping and method for producing the same.” The patent describes GaN/AlGaN transistors with a dielectric layer on the surface of their conductive channels. Donor electrons in the dielectric layer neutralize traps in the channel, helping prevent those traps from slowing the transistors’ high-frequency response. The disclosed manufacturing method uses sputtering to deposit the dielectric layer.

Career Highlights

Mc Carthy’s listed patent focuses on transistor design and fabrication, combining a channel-surface dielectric with a sputtering-based deposition method to address trapping and improve high-frequency response.

Collaborations

The supplied information identifies Jian Xu and Naiqing Zhang as Mc Carthy’s coworkers. The patent description concerns work in the same technical area, but the available details do not specify their roles or contributions.

Conclusion

Lee Mc Carthy’s listed invention presents a dielectric-layer approach to reducing channel trapping in Group III nitride transistors, with the goal of supporting stronger high-frequency performance.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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