Sainte Foy les Lyon, France

Laurent Herard

This inventor holds 1 USPTO granted patent. Top assignee: Stmicroelectronics International N.v.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Laurent Herard. Retrieved from https://idiyas.com/inventor/laurent-herard-olhjgnga

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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Average Co-Inventor Count = 1.0

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Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Laurent Herard and Integrated Circuit Packaging

Introduction

Laurent Herard is an inventor associated with Sainte-Foy-lès-Lyon, France, and STMicroelectronics International N.V. His recorded patent concerns a method for manufacturing integrated circuit packages.

Latest Patents

Herard is credited with 1 patent: “Method for Manufacturing Several Integrated Circuit Packages.” The invention describes an integrated circuit package built around a support substrate with a mounting face and a lateral wall. The wall and mounting face define a cavity that holds an electronic chip, which is electrically connected to contact pads. A sealing structure is bonded to the top of the wall with glue, arranged so that the glue does not spill onto the wall’s outer face. Conductive connections beneath the substrate link to the contact pads through an interconnection network within the substrate.

Career Highlights

The available information associates Herard’s patent work with STMicroelectronics International N.V. The patent focuses on package construction, cavity sealing, and electrical connections for integrated circuits.

Collaborations

Olivier Zanellato and Patrick Laurent are identified as Herard’s coworkers. The supplied information does not specify their roles in the patent or the extent of their collaboration.

Conclusion

Laurent Herard’s recorded invention addresses the design and manufacture of integrated circuit packages, combining chip protection with electrical interconnection.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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