Austin, TX, United States of America

Larry J Grieve

This inventor holds 1 USPTO granted patent. Top assignee: Freescale Semiconductor,inc.. Active years: 2009.


Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 1(Granted Patents)


Company Filing History:


Years Active: 2009

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1 patent (USPTO):Explore Patents

Title: Larry J Grieve: Innovator in Non-Volatile Memory Technology

Introduction

Larry J Grieve is a notable inventor based in Austin, TX, who has made significant contributions to the field of non-volatile memory devices. With a focus on improving the efficiency of memory module verification processes, Grieve's work has implications for various applications in technology.

Latest Patents

Grieve holds a patent for an "In-circuit Vt distribution bit counter for non-volatile memory devices." This innovative patent describes integrated testing components and a testing algorithm that facilitate faster threshold voltage (Vt) distributions during the verification of memory modules. The design includes address and voltage scanning components, along with a bit counter that stores the number of 0's or 1's for a specified voltage. As the addresses are scanned across a range of voltages, the bit counter accumulates the count value, which is then read by Automated Tester Equipment (ATE) for each tested voltage.

Career Highlights

Larry J Grieve is currently employed at Freescale Semiconductor, Inc., where he continues to develop cutting-edge technologies in the semiconductor industry. His work has been instrumental in advancing the capabilities of non-volatile memory devices.

Collaborations

Grieve has collaborated with notable colleagues, including Richard Eguchi and Thomas Jew, who have contributed to his projects and innovations in the field.

Conclusion

Larry J Grieve's contributions to non-volatile memory technology exemplify the impact of innovative thinking in the semiconductor industry. His patent and ongoing work at Freescale Semiconductor, Inc. highlight his role as a key figure in advancing memory module verification processes.

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