Larry G Jones

Title: Innovations by Larry G. Jones in Timing Analysis

Introduction

Larry G. Jones is an accomplished inventor based in San Jose, CA. He has made significant contributions to the field of timing analysis in electronic circuits. His innovative approach focuses on enhancing the efficiency of timing analysis through the reuse of computed delays.

Latest Patents

One of Larry G. Jones's notable patents is titled "Speeding up timing analysis by reusing delays computed for isomorphic subcircuits." This invention provides a system that accelerates timing analysis by reusing delays calculated for isomorphic subcircuits. The system operates by receiving a circuit block in the form of a netlist and subdividing it into a set of subcircuits. These subcircuits are then organized into equivalence classes, which consist of topologically isomorphic subcircuits. During the timing analysis, the system checks if a delay for a subcircuit has already been computed for its equivalence class. If a corresponding delay exists, it is reused; otherwise, the system computes the delay and associates it with the equivalence class for future use.

Career Highlights

Larry G. Jones is currently employed at Synopsys, Inc., where he continues to develop innovative solutions in the field of electronic design automation. His work has been instrumental in improving the efficiency of circuit analysis and design processes.

Collaborations

Larry has collaborated with notable colleagues, including Michael G. Weaver and Mohan Rangan Govindaraj. Their combined expertise has contributed to advancements in the field of timing analysis and electronic circuit design.

Conclusion

Larry G. Jones's contributions to timing analysis through his innovative patent demonstrate his commitment to enhancing electronic design processes. His work continues to influence the industry positively.