Mountain View, CA, United States of America

Lan Luo

This inventor holds 2 USPTO granted patents. Top assignee: Synopsys, Inc.. Active years: 2020-2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Lan Luo. Retrieved from https://idiyas.com/inventor/lan-luo-w61ggarq

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 5.0

ph-index = 1

Forward Citations = 5(Granted Patents)


Company Filing History:


Years Active: 2020-2022

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2 patents (USPTO):Explore Patents

Title: Innovations by Lan Luo in Interposer Designs

Introduction

Lan Luo is an accomplished inventor based in Mountain View, CA, known for his significant contributions to the field of interposer designs. With a total of two patents to his name, he has made strides in automated routing of signal nets, which are crucial for modern electronic devices.

Latest Patents

Luo's latest patents focus on "Routing for length-matched nets in interposer designs." This innovation automates the routing of signal nets defined by their endpoints, known as bumps. The nets and their corresponding bumps are organized into bump groups based on their relative locations and length-matching constraints. Some bump groups may be classified as 'clones,' allowing the routing for one group to be replicated for its clones. This process ensures that the bumps in the two groups maintain the same relative position and adhere to the same length-matching constraints.

Career Highlights

Lan Luo is currently employed at Synopsys, Inc., where he continues to develop innovative solutions in the field of electronic design automation. His work has been instrumental in enhancing the efficiency and effectiveness of interposer designs.

Collaborations

Luo collaborates with talented individuals such as Jitendra Kumar Gupta and Ksenia Roze, who contribute to the innovative environment at Synopsys, Inc.

Conclusion

Lan Luo's contributions to interposer designs through his patents reflect his expertise and commitment to innovation in the field of electronic design. His work continues to influence the industry and pave the way for future advancements.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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