Bend, OR, United States of America

Lachlan Francis Dowling

This inventor holds 1 USPTO granted patent and 3 published patent applications. Top assignee: Nvidia Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Lachlan Francis Dowling. Retrieved from https://idiyas.com/inventor/lachlan-francis-dowling

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Lachlan Francis Dowling: Hardware Accelerator Memory Innovation

Introduction

Lachlan Francis Dowling is an inventor based in Bend, Oregon, and works at NVIDIA Corporation. His patent work addresses how hardware accelerators can use memory efficiently and manage data between on-chip and off-chip storage.

Latest Patents

Dowling is associated with 1 patent: “Firmware-Controlled Memory Binding and Implicit Data Persistence for Hardware Accelerators.” The invention describes systems and methods that check whether an on-chip memory region is already configured for a particular use and reuse it when possible. If no suitable region exists, the system can allocate one and connect it to off-chip memory. Rules can also guide whether data is loaded into on-chip memory or saved back to off-chip memory.

Career Highlights

At NVIDIA Corporation, Dowling’s patent reflects work on memory management for hardware accelerators. The approach aims to support efficient reuse of on-chip memory while coordinating data movement with larger off-chip storage.

Collaborations

Dowling’s listed coworkers include Nan Wang and Rohit Goel. Their shared professional context connects them to NVIDIA’s work in computing technologies.

Conclusion

Lachlan Francis Dowling’s patent focuses on firmware-controlled memory binding and data persistence, addressing practical challenges in how hardware accelerators allocate, reuse, and manage memory.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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