Suwon-si, South Korea

Kyunghee Lee

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Samsung Electronics Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kyunghee Lee. Retrieved from https://idiyas.com/inventor/kyunghee-lee-883xiugt

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Kyunghee Lee and Semiconductor Package Innovation

Introduction

Kyunghee Lee is an inventor based in Suwon-si, South Korea, and is associated with Samsung Electronics. His listed patent concerns semiconductor packaging technology and describes a structure designed to integrate a chip with redistribution layers.

Latest Patents

Lee is credited with 1 patent, titled “Semiconductor package.” The invention describes a package with a chip mounted on a first redistribution structure and a package body covering the chip’s opposing side surfaces. The redistribution structure contains vertically stacked redistribution layers, insulating passivation layers, and vias that electrically connect the layers. Each passivation layer includes a diffusion barrier layer and a warpage control layer, supporting the package’s layered construction and warpage management.

Career Highlights

Lee’s listed patent reflects work in semiconductor packaging, an area involving the electrical interconnection and physical integration of semiconductor chips. The available information associates him with Samsung Electronics but does not provide further details about his role or career history.

Collaborations

Giseung Heo and Seonkyu Kim are identified as Lee’s coworkers. The provided information does not specify their roles in the patent or the nature of their collaboration.

Conclusion

Kyunghee Lee’s listed invention focuses on a semiconductor package that combines redistribution layers, electrical vias, and passivation layers incorporating diffusion barriers and warpage control.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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