DaeJeon, South Korea

Kyoung-wan Park

This inventor holds 2 USPTO granted patents. Top assignee: Electronics and Telecommunications Research Institute. Active years: 2003-2005.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kyoung-wan Park. Retrieved from https://idiyas.com/inventor/kyoung-wan-park-e17d9yc2

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 50.0

Average Co-Inventor Count = 3.4

ph-index = 2

Forward Citations = 8(Granted Patents)


Company Filing History:


Years Active: 2003-2005

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2 patents (USPTO):Explore Patents

Title: Innovations by Kyoung-wan Park: Contributions to Semiconductor Technology

Introduction

Kyoung-wan Park is a notable inventor from Daejon, South Korea, recognized for his contributions to the field of semiconductor technology. With two patents to his name, he has been instrumental in developing innovative manufacturing methods that enhance the performance and efficiency of semiconductor devices.

Latest Patents

Kyoung-wan Park’s recent patents include the following innovations:

1. **Method of Manufacturing Er-doped Silicon Nano-dot Array and Laser Ablation Apparatus Used Therein**: This invention involves a method for producing Er-doped silicon nano-dot arrays. The process begins with the preparation of a target that contains both silicon and erbium regions. A silicon substrate is then positioned opposite the target, where laser light is directed to generate a plume containing ablated silicon and erbium. This plume is utilized to deposit an Er-doped silicon film onto the substrate, which is subsequently patterned for further applications.

2. **Method of Fabricating MOS Transistor Having Shallow Source/Drain Junction Regions**: This patent describes a method for fabricating MOS transistors with shallow source and drain junctions. The process involves forming a diffusion source layer on a semiconductor substrate with gate patterns already established. Impurities are implanted into the diffusion source layer multiple times in varying directions, avoiding dislocation and controlling the impurity concentration without damaging the substrate's crystal structure. The resultant impurities diffuse into the semiconductor substrate, creating shallow source and drain junction regions through a self-alignment method.

Career Highlights

Kyoung-wan Park is affiliated with the Electronics and Telecommunications Research Institute, a leading organization focused on technological advancements in electronics and telecommunications. His innovative work on semiconductor manufacturing methodologies has significant implications for improving device performance.

Collaborations

Throughout his career, Kyoung-wan Park has collaborated with esteemed colleagues, including Jeong-sook Ha and Seung-Min Park. These partnerships have played a vital role in fostering innovation and enhancing the research environment at their institution.

Conclusion

Kyoung-wan Park’s contributions through his patents reflect a dedication to advancing semiconductor technology. His innovative methods for manufacturing Er-doped silicon nano-dot arrays and fabricating MOS transistors showcase his commitment to improving efficiency and performance in the field. As technology evolves, inventions like those of Kyoung-wan Park continue to pave the way for future advancements in electronics and telecommunications.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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