San Jose, CA, United States of America

Kuo-Tsai Li

This inventor holds 3 USPTO granted patents. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2006-2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kuo-Tsai Li. Retrieved from https://idiyas.com/inventor/kuo-tsai-li

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 66.7

Average Co-Inventor Count = 2.6

ph-index = 2

Forward Citations = 10(Granted Patents)


Company Filing History:


Years Active: 2006-2015

Loading Chart...
3 patents (USPTO):Explore Patents

Title: Kuo-Tsai Li: Innovator in Integrated Circuit Design

Introduction

Kuo-Tsai Li is a prominent inventor based in San Jose, CA (US). He has made significant contributions to the field of integrated circuit design, holding a total of 3 patents. His work focuses on enhancing the efficiency and accuracy of integrated circuit systems.

Latest Patents

Kuo-Tsai Li's latest patents include innovative methods for designing integrated circuits. One of his notable patents is titled "Methods of designing integrated circuits and systems thereof." This method involves performing a pre-layout simulation of the integrated circuit using a netlist generated from a process design kit (PDK) file. The PDK file contains various device model cards assigned to multiple devices, including a first device with at least one parasitic diode associated with an isolation well. The design layout of the integrated circuit is generated based on the results of the pre-layout simulation.

Another significant patent is the "High accuracy and universal on-chip switch matrix testline." This patent presents a testline structure designed for integrated circuit tests. The structure features an array of testline pads formed in the scribe line area or integrated circuit die area on a semiconductor substrate. It includes a select circuit that connects one of the test devices, enabling access to numerous test devices through the same number of pads as a conventional testline. This innovation allows for conducting parametric, reliability, and functional tests efficiently.

Career Highlights

Kuo-Tsai Li is currently employed at Taiwan Semiconductor Manufacturing Company Limited, where he continues to push the boundaries of integrated circuit technology. His expertise and innovative approach have made him a valuable asset in the semiconductor industry.

Collaborations

Throughout his career, Kuo-Tsai Li has collaborated with notable colleagues, including Tseng Chin Lo and Chi-Chiang Lin. These collaborations have further enriched his work and contributed to advancements in integrated circuit design.

Conclusion

Kuo-Tsai Li is a distinguished inventor whose contributions to integrated circuit design have had a lasting impact on the industry. His innovative patents and collaborative efforts continue to shape the future of semiconductor technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…