Kunio Sakamoto

Title: Kunio Sakamoto: Semiconductor Packaging Inventor

Introduction

Kunio Sakamoto is an inventor associated with Oita, Japan, and Texas Instruments Corporation. His patent work addresses semiconductor packaging, particularly the design of substrates used to mount semiconductor chips. The available information lists 1 patent for him.

Latest Patents

Sakamoto’s listed patent is “Semiconductor Chip Mounting Substrate and Semiconductor Device Using It.” The invention describes a flexible substrate with a chip-mounting region, conductor patterns electrically connected to the semiconductor chip, and an insulation pattern positioned partly within the mounting region. The design aims to reduce substrate warping that can result from the insulation pattern’s curing contraction during manufacture. By placing the insulation pattern between the chip and conductor patterns in part of the mounting region, the substrate supports the chip while addressing this deformation.

Career Highlights

Sakamoto’s documented patent contribution focuses on a practical challenge in semiconductor-device construction: maintaining substrate stability as insulating materials are formed and cured. The patent connects this structural approach with the assembly of a semiconductor chip and its electrical connections.

Collaborations

Sakamoto’s listed coworkers include Kensho Murata and Makoto Yoshino. The available information identifies them as coworkers but does not specify their roles in the patent.

Conclusion

Kunio Sakamoto’s listed invention concerns a chip-mounting substrate designed to reduce warping and support reliable semiconductor-device assembly.