Kun-Chih Chan

Title: Innovations of Kun-Chih Chan in Wafer-Level Testing

Introduction

Kun-Chih Chan is a notable inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of semiconductor testing, particularly in wafer-level testing methods. With a total of 2 patents to his name, Chan's work has advanced the efficiency and effectiveness of testing processes in the industry.

Latest Patents

Chan's latest patents include a "Wafer-level testing method for singulated 3D-stacked chip cubes" and a "Method for wafer-level testing diced multi-chip stacked packages." The first patent discloses a method for testing multiple singulated 3D-stacked chip cubes using adjustable wafer maps. This innovative approach allows for the optimization of pick-and-place positions on a carrier wafer, enhancing productivity by minimizing unnecessary adjustments during testing. The second patent focuses on wafer-level testing for diced multi-chip stacked packages, which includes chips with vertically electrical connections. This method facilitates the integration of wafer-level testing into TSV packaging processes, streamlining the overall testing procedure.

Career Highlights

Kun-Chih Chan is currently employed at Powertech Technology Inc., a leading company in semiconductor packaging and testing. His work at Powertech has allowed him to apply his innovative ideas in a practical setting, contributing to the company's reputation for excellence in the industry.

Collaborations

Chan has collaborated with notable colleagues such as Shin-Kung Chen and Kai-Jun Chang. Their combined expertise has fostered a productive environment for innovation and development in semiconductor testing technologies.

Conclusion

Kun-Chih Chan's contributions to wafer-level testing methods have significantly impacted the semiconductor industry. His innovative patents and collaborative efforts continue to drive advancements in testing efficiency and effectiveness.