Kun-Cheng Wu

Title: Kun-Cheng Wu: Innovator in Analog IP Characterization

Introduction

Kun-Cheng Wu is a prominent inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of analog integrated circuits, holding a total of 7 patents. His work focuses on methodologies that enhance the efficiency and accuracy of analog IP characterization.

Latest Patents

One of his latest patents is titled "Methodology and system for setup/hold time characterization of analog IP." This innovation provides a fast methodology and system to characterize setup and hold times for analog IPs. Instead of simulating entire IPs, partial circuits of clock and data paths are simulated. This approach includes multi-path searching of hierarchical SPICE netlists to reduce the circuit subset and merge the paths of clock and data pins for effective characterization. Another notable patent is the "Method for reducing standard delay format file size." This method involves removing state-dependent descriptions in cell descriptions of the SDF file that are not intended for use, thereby reducing the file size without affecting simulation results.

Career Highlights

Kun-Cheng Wu has worked with esteemed organizations such as the Industrial Technology Research Institute and Faraday Technology Corporation. His experience in these institutions has allowed him to refine his skills and contribute to significant advancements in the field of analog technology.

Collaborations

Throughout his career, Kun-Cheng Wu has collaborated with notable colleagues, including Ruey-Liang Ma and Chia-Chang Hsu. These collaborations have fostered innovation and have been instrumental in the development of his patented methodologies.

Conclusion

Kun-Cheng Wu's contributions to analog IP characterization through his innovative patents and collaborations highlight his role as a key figure in the field. His work continues to influence advancements in integrated circuit design and characterization methodologies.