The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 2009
Filed:
Dec. 08, 2006
Hanping Chen, Taoyuan County, TW;
Chih-yang Peng, Taoyuan County, TW;
Alvin Hsin-hung Chen, Kaohsiung, TW;
Jia-jio Huang, Hsinchu, TW;
Jim Jyh-herng Wang, Hsinchu County, TW;
Kun-cheng Wu, Hsinchu, TW;
Hanping Chen, Taoyuan County, TW;
Chih-Yang Peng, Taoyuan County, TW;
Alvin Hsin-Hung Chen, Kaohsiung, TW;
Jia-Jio Huang, Hsinchu, TW;
Jim Jyh-Herng Wang, Hsinchu County, TW;
Kun-Cheng Wu, Hsinchu, TW;
Faraday Technology Corp., Hsin-Chu, TW;
Abstract
A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The partial circuits include all those paths of clock pin and data input pins before reaching first level DFF. This methodology includes multi-path searching of hierarchical SPICE netlist for the path of clock pin and data pins, so as to reduce the circuit subset, merge the paths of clock pin and the data pins, and characterize the setup/hold time for the analog IP. The paths of data pins and clock pin before DFF are used for setup/hold time characterization.