New Taipei City, Taiwan

Kuan-Chih Chen

This inventor holds 1 USPTO granted patent. Top assignee: Macronix International. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kuan-Chih Chen. Retrieved from https://idiyas.com/inventor/kuan-chih-chen-lft3ea0x

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Kuan-Chih Chen: Memory Device Innovation

Introduction

Kuan-Chih Chen is an inventor based in New Taipei City, Taiwan. His work includes a patent concerning memory devices and their programming methods. Chen is associated with Macronix International and holds 1 patent in the information provided.

Latest Patents

Chen’s patent, “Memory Device, Operation Method of the Same and Memory System,” describes a memory device with a memory array, a voltage generator, and an array control circuit. The memory array contains first and second arrays.

During a programming stage, the control circuit directs the voltage generator to produce a first control voltage and creates a temporary address. The first array then stores storage data and address data in a first programming step. During an idle stage, the circuit directs the generator to produce a second control voltage, and the second array stores storage data in a second programming step using the address data. The voltage used in the first programming step is greater than the voltage used in the second.

Career Highlights

Chen’s patent focuses on coordinating memory-array operations with different control voltages and programming stages. This approach distinguishes the handling of storage and address data across the device’s two arrays.

Collaborations

The provided information associates Chen with Macronix International. It does not specify particular co-inventors or other collaborators for the patent.

Conclusion

Kuan-Chih Chen’s patent documents an approach to memory-device programming that uses separate arrays, staged operations, and different voltage levels.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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