Nagoya, Japan

Kouji Igarashi

This inventor holds 1 USPTO granted patent. Top assignee: Mitsui Chemicals, Inc.. Active years: 2007.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kouji Igarashi. Retrieved from https://idiyas.com/inventor/kouji-igarashi-do1fbxss

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 5.0

ph-index = 1


Company Filing History:


Years Active: 2007

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1 patent (USPTO):Explore Patents

Title: Kouji Igarashi - Innovator in Semiconductor Protection

Introduction

Kouji Igarashi is a notable inventor based in Nagoya, Japan. He has made significant contributions to the field of semiconductor technology, particularly in the area of protective materials.

Latest Patents

Igarashi holds a patent for a "Pressure sensitive adhesive film for protection of semiconductor wafer surface and method of protecting semiconductor wafer with the pressure sensitive adhesive film." This invention relates to a surface protecting adhesive film designed for semiconductor wafers. The adhesive layer has a storage elastic modulus ranging from 1×10 Pa to 1×10 Pa at 150°C, with a thickness between 3 µm and 100 µm. The base film, which has a melting point of at least 200°C and a thickness of 10 µm to 200 µm, ensures that the semiconductor wafer can be ground without breaking or contamination, even when thinned to as low as 100 µm.

Career Highlights

Kouji Igarashi is currently employed at Mitsui Chemicals, Inc., where he continues to innovate in the field of semiconductor materials. His work has been instrumental in enhancing the reliability and performance of semiconductor devices.

Collaborations

Igarashi has collaborated with notable colleagues such as Yoshihisa Saimoto and Makoto Kataoka, contributing to advancements in semiconductor technology.

Conclusion

Kouji Igarashi's innovative work in semiconductor protection demonstrates his commitment to advancing technology in this critical field. His contributions are vital for the ongoing development of reliable semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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