Kawasaki, Japan

Kouichi Yoshida

This inventor holds 1 USPTO granted patent. Top assignee: Panasonic Corporation. Active years: 2010.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kouichi Yoshida. Retrieved from https://idiyas.com/inventor/kouichi-yoshida-7d5j5qm8

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 4.0

ph-index = 1


Company Filing History:


Years Active: 2010

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1 patent (USPTO):Explore Patents

Title: Kouichi Yoshida: Semiconductor Device Inventor

Introduction

Kouichi Yoshida is an inventor associated with Kawasaki, Japan, and Panasonic Corporation. His work includes a patent for a semiconductor device designed to help prevent unwanted contact between electrodes on a film substrate and the edges of a mounted semiconductor element. His listed patent portfolio includes 1 patent.

Latest Patents

Yoshida’s listed patent, “Semiconductor device,” describes an insulating protection part formed at a selected position on the surface of a semiconductor element facing the electrodes on a film substrate. The design also specifies a gap of at least 10 micrometers between the semiconductor element and the substrate. These features are intended to reliably prevent contact between the electrodes and the element’s edge parts during mounting.

Career Highlights

Yoshida is associated with Panasonic Corporation, a company active in electronics and technology. The available information identifies his semiconductor-device patent but does not provide further details about his role, career history, or the patent’s filing and grant dates.

Collaborations

Daido Komyoji and Kazushi Higashi are identified as Yoshida’s coworkers. The available information does not specify their roles in the patent or describe particular collaborative projects.

Conclusion

Kouichi Yoshida’s listed invention addresses a practical mounting concern in semiconductor devices by combining an insulating protection feature with a defined minimum gap. This patent reflects his documented contribution to semiconductor technology at Panasonic Corporation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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