This inventor holds 1 USPTO granted patent. Top assignee: Globalfoundries Inc.. Active years: 2020.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2020
Title: Inventor Spotlight: Kok Hin Teo
Introduction
Kok Hin Teo is an innovative inventor based in Schenectady, NY, known for his contributions to semiconductor manufacturing. He has developed a unique patented system that revolutionizes failure analysis processes in the production of integrated circuit chips.
Latest Patents
Teo holds a significant patent titled "System and method for performing failure analysis using virtual three-dimensional imaging." This patent discloses a method where an in-line optical inspection is conducted to capture a two-dimensional image of defects on a semiconductor wafer. The 2D image is then transformed into a virtual three-dimensional image, allowing for a more accurate assessment of the defect's nature. By employing techniques to assess the topography of the surface from the 2D image, and filtering out any anomalies, the resulting 3D image facilitates in-line failure analysis that is significantly faster than traditional off-line methods. This innovation supports real-time advanced process control (APC), thereby enhancing the efficiency of semiconductor manufacturing.
Career Highlights
Teo has made substantial contributions while working at GlobalFoundries Inc., a prominent semiconductor manufacturing company. His expertise in failure analysis and optical imaging technology has played a critical role in advancing the capabilities of production processes within the industry.
Collaborations
Throughout his career, Kok Hin Teo has collaborated with notable colleagues, including Jay A. Mody and Jeffrey B. Riendeau. These partnerships have enriched the inventive environment at GlobalFoundries Inc. and have fostered the development of cutting-edge technologies in semiconductor manufacturing.
Conclusion
Kok Hin Teo's innovative approach to failure analysis through virtual three-dimensional imaging represents a significant advancement in the semiconductor manufacturing sector. His patent not only enhances the efficacy of in-line testing but also plays a pivotal role in maintaining quality and efficiency in the production of integrated circuit chips. As technology continues to evolve, Teo's contributions will undoubtedly leave a lasting impact on the industry.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
