This inventor holds 2 USPTO granted patents. Top assignees: Cadence Design Systems, Inc., Silicon Perspective Corporation. Active years: 2003.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:

Years Active: 2003
Title: Innovations by Kit-Lam Cheong
Introduction
Kit-Lam Cheong is an accomplished inventor based in Palo Alto, CA. He holds 2 patents that contribute significantly to the field of integrated circuit design. His work focuses on improving the efficiency and effectiveness of IC layout systems.
Latest Patents
One of his notable patents is the "Scalable, partitioning integrated circuit layout system." This innovative system modifies a netlist describing an IC as a hierarchy of circuit modules. It combines clusters of cells to form larger cells, reducing the overall number of cells in the IC. This reduction leads to a decrease in the time required to generate an IC layout. The system generates a trial layout based on the modified netlist and estimates the substrate area required for each module. It divides the IC design into several partitions and creates a partition plan that allocates substrate space based on the estimated requirements. Additionally, it creates a timing budget that allocates signal path timing constraints among the partitions. Each IC partition is then laid out independently to satisfy its spatial and timing constraints, resulting in a complete IC layout.
Another significant patent is the "Method for generating a partitioned IC layout." This method quickly produces a trial layout that satisfies various spatial and power constraints, while timing constraints are not initially considered. The trial layout serves as a basis for estimating the sizes and positions of substrate areas needed for the IC modules. The design is divided into several partitions based on the proximity of modules in the trial layout. A floor plan is created to impose spatial constraints on each partition, and a timing budget allocates timing constraints based on delay estimates. The partitions are then placed and routed in accordance with the imposed constraints.
Career Highlights
Kit-Lam Cheong has worked with notable companies such as Silicon Perspective Corporation and Cadence Design Systems, Inc. His experience in these organizations has allowed him to refine his skills and contribute to advancements in integrated circuit technology.
Collaborations
He has collaborated with talented individuals in the field, including Wei-Jin Dai and Hsi-Chuan Chen. These collaborations have further enriched his work and innovations.
Conclusion
Kit-Lam Cheong's contributions to integrated circuit design through his patents and career experiences highlight his significant role in the field. His innovative approaches continue to influence the development of efficient IC layout systems.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile