Ker-Ching Liu

Title: Innovations by Ker-Ching Liu

Introduction

Ker-Ching Liu is a notable inventor based in San Jose, California. He has made significant contributions to the field of field programmable gate arrays (FPGAs). His innovative work has led to the development of a patented technology that enhances the performance of clock networks in FPGAs.

Latest Patents

Ker-Ching Liu holds a patent for a "Clock network for field programmable gate array." This invention features a clock network that includes a first clock bus extending across the chip in a first dimension. The design allows for a clock pad to be coupled to the first clock bus, enabling the clock network to be driven from either the clock pad or a selected logic cell. To improve the speed of the clock network, the first clock bus is segmented, allowing only a short piece of the bus to be used for high-speed applications.

Career Highlights

Ker-Ching Liu is currently employed at QuickLogic Corporation, where he continues to innovate in the field of programmable logic devices. His work has been instrumental in advancing the capabilities of FPGAs, making them more efficient and faster.

Collaborations

He has collaborated with notable colleagues such as Mukesh T Lulla and David D Eaton, contributing to various projects that enhance the functionality of programmable devices.

Conclusion

Ker-Ching Liu's contributions to the field of field programmable gate arrays through his innovative patent demonstrate his expertise and commitment to advancing technology. His work continues to influence the industry positively.