This inventor holds 1 USPTO granted patent. Top assignee: Teradyne, Inc.. Active years: 1990.
Company Filing History:
Years Active: 1990
Title: Innovations by Kenneth C Choy in Semiconductor Timing Analysis
Introduction
Kenneth C Choy is an accomplished inventor based in Fremont, CA (US). He has made significant contributions to the field of semiconductor digital circuits, particularly in the area of static timing analysis. His innovative work has led to the development of a unique patent that enhances the performance and reliability of logic designs.
Latest Patents
Kenneth C Choy holds a patent for "Static timing analysis of semiconductor digital circuits." This invention introduces a time verification scheme that operates without input stimulus to calculate delays along circuit paths, including logic elements or cells from initial input to final output. The delay calculations take into account cell-dependent, layout-dependent, and environmental-dependent factors. This comprehensive approach allows for accurate response delay assessments on both rising and falling signals. The invention also considers capacitance loading, temperature-dependency, and voltage-dependency to provide detailed output histograms and reports regarding overall performance and timing violations of proposed logic designs.
Career Highlights
Kenneth is currently employed at Teradyne, Inc., where he continues to apply his expertise in semiconductor technology. His work has been instrumental in advancing the capabilities of digital circuits, ensuring that they meet the rigorous demands of modern electronics.
Collaborations
Throughout his career, Kenneth has collaborated with notable colleagues, including John J Zasio and Darrell R Parham. These partnerships have fostered a collaborative environment that encourages innovation and the sharing of ideas.
Conclusion
Kenneth C Choy's contributions to semiconductor digital circuits through his patent on static timing analysis exemplify his commitment to innovation in the field. His work not only enhances the performance of logic designs but also sets a foundation for future advancements in semiconductor technology.