Kokubunji, Japan

Kazushige Ayukawa

This inventor holds 55 USPTO granted patents and 2 published patent applications, primarily in Semiconductor Devices (CPC class 3652). Top assignees: Hitachi, Ltd., Renesas Technology Corp., Renesas Electronics Corporation. Active years: 1997-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kazushige Ayukawa. Retrieved from https://idiyas.com/inventor/kazushige-ayukawa

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 55 

% Patents Active = 65.5

Average Co-Inventor Count = 3.1

ph-index = 16

Forward Citations = 1,052(Granted Patents)

Forward Citations (Not Self Cited) = 1,028(Dec 10, 2025)


Inventors with similar research interests:


Company Filing History:


Years Active: 1997-2014

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Areas of Expertise:
Semiconductor Device
Multi-Chip
Non-Volatile Memory
Random Access Memory
Memory Controller
Data Processing System
Memory Module
Integrated Circuit
Dynamic Random Access Memory
Flash Memory
Address Allocation
Logic Circuit
55 patents (USPTO):Explore Patents

Title: Kazushige Ayukawa: A Pioneer in Semiconductor Innovations

Introduction

Kazushige Ayukawa is a distinguished inventor based in Kokubunji, Japan, known for his significant contributions to the field of semiconductor technology. With an impressive portfolio of 55 patents, Ayukawa has played a vital role in advancing memory storage solutions and enhancing the efficiency of semiconductor devices.

Latest Patents

Among his latest inventions are two notable patents that showcase his innovative approach to semiconductor device design:

1. **Semiconductor device including multi-chip**: This invention aims to implement a memory system with a large storage capacity and reduced data retention current. It modularizes non-volatile memory, SRAM, DRAM, and a control circuit into a single package. The control circuit is responsible for assigning addresses to the SRAM and DRAM while retaining long-term data in the SRAM. The design includes multiple banks within the DRAM, divided into two sets and mapped to the same address space, with sets being refreshed alternately. By stacking and wiring several chips using BGA and chip-to-chip bonding methods, Ayukawa's patent presents an innovative solution for memory architecture.

2. **Semiconductor device with non-volatile memory and random access memory**: This invention features a semiconductor device that combines large-capacity non-volatile memory with random access memory (RAM). The access time of the device matches that of the RAM, which is achieved by transferring FLASH data to the DRAM before access. The system includes a control circuit that connects both the FLASH and the DRAM, ensuring synchronized data storage and retrieval, thereby optimizing performance.

Career Highlights

Kazushige Ayukawa's illustrious career includes noteworthy stints at prominent companies such as Hitachi, Ltd. and Renesas Technology Corporation. His work has consistently intersected with cutting-edge innovations in semiconductor technology, making him a prominent figure in this field.

Collaborations

Throughout his career, Ayukawa has collaborated with esteemed colleagues, including Seiji Miura and Takao Watanabe. These partnerships have further bolstered his research and development efforts, leading to groundbreaking advancements in memory technology.

Conclusion

Kazushige Ayukawa's contributions to semiconductor innovations are pivotal in shaping the future of memory storage solutions. With a demonstrated commitment to enhancing device efficiency and storage capacity, Ayukawa continues to influence the semiconductor industry significantly through his numerous patents and collaborative efforts. His work serves as an inspiration for future generations of inventors and engineers striving to push the boundaries of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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