Hadano, Japan

Kazunobu Morimoto

This inventor holds 3 USPTO granted patents. Top assignees: Hitachi, Ltd., Hitachi Computer Electronics Co., Ltd.. Active years: 1999-2003.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kazunobu Morimoto. Retrieved from https://idiyas.com/inventor/kazunobu-morimoto

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.8

ph-index = 3

Forward Citations = 31(Granted Patents)


Location History:

  • Hadano, JP (1999)
  • Zama, JP (2003)

Company Filing History:


Years Active: 1999-2003

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3 patents (USPTO):Explore Patents

Title: Kazunobu Morimoto: Innovator in Logic Division and Design Support Systems

Introduction

Kazunobu Morimoto is a notable inventor based in Hadano, Japan. He has made significant contributions to the field of logic division and design support systems, holding a total of 3 patents. His work focuses on enhancing the efficiency and speed of logic emulation systems.

Latest Patents

Morimoto's latest patents include a logic dividing method, a logic dividing system, and a recording medium for storing a logic dividing program. The logic emulation system he developed aims to provide a high-speed logic dividing and module wiring system for operating logic related to external interface signals. This system reads information on assignments of external interface signals during the logic division process. It assigns logic related to these signals directly to field programmable gate arrays connected to the corresponding connector pins. Additionally, the system checks delays after the division of a logic circuit to assess the criticality of each interface signal, ensuring efficient wiring based on these levels of criticality.

Another significant patent is a design support system and method for executing logic verification. This system enhances work management, progress state management, and logic quality management during the verification process. It stores management information for each verification item, ensuring that logic simulation is executed only when all prerequisite verification items have been confirmed.

Career Highlights

Throughout his career, Morimoto has worked with prominent companies such as Hitachi, Ltd. and Hitachi Computer Electronics Co., Ltd. His experience in these organizations has contributed to his expertise in logic design and verification processes.

Collaborations

Morimoto has collaborated with notable colleagues, including Osamu Tada and Mototsugu Fujii. Their combined efforts have further advanced the field of logic division and design support systems.

Conclusion

Kazunobu Morimoto's innovative work in logic division and design support systems has made a significant impact in the field. His patents reflect a commitment to improving the efficiency and effectiveness of logic verification processes.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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