The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 1999

Filed:

May. 29, 1996
Applicant:
Inventors:

Kazunobu Morimoto, Hadano, JP;

Shun Ishiyama, Hadano, JP;

Osamu Tada, Hadano, JP;

Satoshi Fujiwara, Hadano, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06G / ;
U.S. Cl.
CPC ...
701-1 ; 364488 ; 364578 ; 364489 ; 395500 ;
Abstract

A design support system for executing logic verification so as to perform work management, progress state management and logic quality management efficiently in a logic verification process and so as to improve the man-hour for development and the throughput of computer resources. For every verification item to be executed, management information including a verification item number for identifying a verification item, confirmation information for indicating the fact that no failure has been confirmed in the verification item, a prerequisite verification item number for identifying another verification item required to be confirmed as a prerequisite for the verification item is stored in a memory of the system. Before execution of logic simulation which is performed by giving test data for logic verification of the design data to the design data as a subject of logic verification, data in the memory are searched so that logic simulation is executed in the case where all verification items as prerequisites for verification items to be executed have been already confirmed.


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