IDiyas

For the Inventor, By the Inventor

Tokyo, Japan

Kazuko Yamamoto

USPTO Granted Patents = 14

Average Co-Inventor Count = 3.6

ph-index = 5

Forward Citations = 569(Granted Patents)


Location History:

  • Minato-ku, JP (2003)
  • Tokyo, JP (1998 - 2004)

Company Filing History:

goldMedal14 out of 52,711 
 
Kabushiki Kaisha Toshiba
 patents

Years Active: 1998-2004

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14 patents (USPTO):Explore Patents
1. 6806941 - Pattern forming method and pattern forming apparatus (2004-10-19),
2. 6637010 - Method and program for processing design pattern of semiconductor integrated circuit (2003-10-21),
3. 6622297 - Pattern correcting method and pattern verifying method (2003-09-16),
4. 6335145 - Pattern forming method and pattern forming apparatus (2002-01-01),
5. 6249900 - Method of designing an LSI pattern to be formed on a specimen with a bent portion (2001-06-19),
6. 6243855 - Mask data design method (2001-06-05),
7. 6165652 - Pattern forming method and pattern forming apparatus (2000-12-26),
8. 6110647 - Method of manufacturing semiconductor device (2000-08-29),
9. 6077310 - Optical proximity correction system (2000-06-20),
10. 6060368 - Mask pattern correction method (2000-05-09),
11. 6040114 - Pattern forming method (2000-03-21),
12. 6004701 - Method for designing Levenson photomask (1999-12-21),
13. 5879844 - Optical proximity correction method (1999-03-09),
14. 5795683 - Method and a system for designing a photomask for use in manufacture of (1998-08-18),

Title: Innovator Spotlight: Kazuko Yamamoto - Revolutionizing Semiconductor Device Patterns.

Introduction:

Kazuko Yamamoto, a distinguished inventor based in Tokyo, Japan, is making significant strides in the field of semiconductor device patterns. With a total of 14 patents under his belt, Yamamoto's innovative approach is reshaping the way we perceive pattern formation in the semiconductor industry.

Latest Patents:

Yamamoto's recent patents showcase his expertise in pattern forming methods for semiconductor devices. One of his groundbreaking inventions includes a method for forming patterns on a substrate using charged particle beams or electromagnetic beams. This technique allows for precise shaping of exposed regions with optimal efficiency and accuracy.

Another notable patent by Yamamoto is a method and program for processing design patterns of semiconductor integrated circuits. This innovative process involves optimizing the design pattern data by aggregating lower-level cells into higher-level cells, thus enhancing the overall efficiency of semiconductor circuit fabrication.

Career Highlights:

As a valuable member of Kabushiki Kaisha Toshiba, a prominent technology company, Yamamoto's contributions have been instrumental in driving forward the company's advancements in semiconductor device fabrication. His expertise and dedication have positioned him as a key player in the innovation ecosystem within the organization.

Collaborations:

Yamamoto has collaborated with esteemed colleagues such as Soichi Inoue and Sachiko Kobayashi. Together, they have worked on various projects that have pushed the boundaries of semiconductor technology, fostering a culture of innovation and excellence within their team.

Conclusion:

In conclusion, Kazuko Yamamoto's remarkable journey as an inventor in the realm of semiconductor devices exemplifies a commitment to excellence and ingenuity. His patented inventions and collaborative efforts continue to shape the future of semiconductor technology, solidifying his legacy as a trailblazer in the industry.

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