Sagamihara, Japan

Katsunari Murayama

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Micron Technology Incorporated. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Katsunari Murayama. Retrieved from https://idiyas.com/inventor/katsunari-murayama

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Katsunari Murayama: Semiconductor Memory Device Inventor.

Introduction

Katsunari Murayama is an inventor associated with Sagamihara, Japan, and Micron Technology Incorporated. His patent work concerns semiconductor memory architecture and the circuitry used to control memory cells.

Latest Patents

Murayama is credited with 1 patent: “Semiconductor Device Having Row Decoder Circuit.” The disclosed apparatus places first and second memory cell arrays alongside an intermediate region containing sub word line drivers, main word line drivers, and level shift circuits. The level shift circuits provide voltage-level-shifted signals to the main word line drivers, supporting the row-decoding arrangement.

Career Highlights

Murayama’s listed invention addresses the organization and operation of row decoder components in a semiconductor device. His work is associated with Micron Technology Incorporated, a company active in memory and semiconductor technologies.

Collaborations

His listed coworkers include Mamoru Nishizaki and Manami Mizukane. Their names provide context for the professional network associated with his patent record.

Conclusion

Katsunari Murayama’s patent reflects a focused contribution to semiconductor memory design, particularly the arrangement of row decoder circuitry and its supporting voltage-level-shifting components.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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