logo

For the Inventor, By the Inventor

Kaohsiung, Taiwan

Kao-Yu Hsu

This inventor holds 9 USPTO granted patents. Top assignee: Advanced Semiconductor Engineering, Inc.. Active years: 2001-2002.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kao-Yu Hsu. Retrieved from https://idiyas.com/inventor/kao-yu-hsu-wqmc0wt3

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 9

% Patents Active = 100.0

Average Co-Inventor Count = 2.3

ph-index = 7

Forward Citations = 492(Granted Patents)


Location History:

  • Hsien, TW (2001)
  • Kaohsiung Hsien, TW (2001 - 2002)

Company Filing History:

goldMedal9 out of 1,971 
 
Advanced Semiconductor Engineering, Inc.
 patents

Years Active: 2001-2002

Loading Chart...
9 patents (USPTO):Explore Patents
1. 6482675 - Substrate strip for use in packaging semiconductor chips and method for making the substrate strip (2002-11-19),
2. 6462421 - Multichip module (2002-10-08),
3. 6380002 - Method for fabricating a flexible substrate based ball grid array (BGA) package (2002-04-30),
4. 6338813 - Molding method for BGA semiconductor chip package (2002-01-15),
5. 6316828 - Structure of a solder mask for the circuit module of a BGA substrate (2001-11-13),
6. 6291271 - Method of making semiconductor chip package (2001-09-18),
7. 6271057 - Method of making semiconductor chip package (2001-08-07),
8. 6262490 - Substrate strip for use in packaging semiconductor chips (2001-07-17),
9. 6242815 - Flexible substrate based ball grid array (BGA) package (2001-06-05),

Title: Innovations by Kao-Yu Hsu in Semiconductor Packaging

Introduction

Kao-Yu Hsu is a prominent inventor based in Kaohsiung Hsien, Taiwan. He has made significant contributions to the field of semiconductor packaging, holding a total of 9 patents. His work focuses on enhancing the efficiency and effectiveness of semiconductor chip packaging methods.

Latest Patents

One of Hsu's latest patents is for a substrate strip designed for use in packaging semiconductor chips. This flexible substrate strip consists of multiple substrate units that are specifically adapted for mounting semiconductor chips. The innovative design includes a series of degating regions that ensure the edges of mold runners and gates fit entirely within these regions during the encapsulation process. This design minimizes adhesive force issues between the encapsulant material and the substrate, enhancing the overall reliability of the packaging.

Another notable patent is for a multichip module that features both wire bonding and flip-chip bonding techniques. This module allows for two chips of the same type to be mounted on opposite sides of a substrate, with both chips oriented face up. This design facilitates a more efficient circuit layout, as the bonding pads on both chips can conform to the same address assignment, allowing for common conductive traces to be connected through plated through holes.

Career Highlights

Kao-Yu Hsu is currently associated with Advanced Semiconductor Engineering, Inc., a leading company in the semiconductor industry. His work has significantly impacted the development of advanced packaging solutions, making him a key figure in this field.

Collaborations

Hsu has collaborated with notable colleagues such as Chun-Chi Lee and Shih Chang Lee, contributing to various innovative projects within the semiconductor sector.

Conclusion

Kao-Yu Hsu's contributions to semiconductor packaging through his innovative patents demonstrate his expertise and commitment to advancing technology in this field. His work continues to influence the industry and improve the efficiency of semiconductor chip packaging methods.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…