San Jose, CA, United States of America

Kang-rong Chiang

This inventor holds 1 USPTO granted patent. Top assignee: Lsi Logic Corporation. Active years: 2002.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kang-rong Chiang. Retrieved from https://idiyas.com/inventor/kang-rong-chiang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 1


Company Filing History:


Years Active: 2002

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1 patent (USPTO):Explore Patents

Title: Kang-rong Chiang and Rapid Wafer Bumping

Introduction

Kang-rong Chiang is an inventor associated with San Jose, California, and LSI Logic Corporation. His patent work addresses wafer bumping, a process used to form conductive connections on semiconductor wafers.

Latest Patents

Chiang is credited with 1 patent: “Method of Rapid Wafer Bumping.” The invention describes spreading electrically conductive paste over a surface containing multiple electrical contacts, then directing an energy beam at a beam-paste interaction volume. This bonds part of the paste layer to at least one contact, forming a wafer bump.

Career Highlights

Chiang’s listed patent reflects work on a method for forming wafer bumps through the localized application of energy. The patent identifies LSI Logic Corporation as the company associated with his work.

Collaborations

Chiang is listed as a coworker of Senol Pekin. The available information does not specify further details about their collaboration.

Conclusion

Kang-rong Chiang’s patent focuses on a rapid wafer-bumping method that bonds conductive paste to electrical contacts using an energy beam.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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