Kanan Garg

Title: Kanan Garg: Innovator in Semiconductor Technology

Introduction

Kanan Garg is a notable inventor based in Plano, Texas, recognized for his contributions to semiconductor technology. He has made significant strides in enhancing the performance of NMOS and PMOS transistors through innovative methods.

Latest Patents

Kanan Garg holds a patent titled "Stress memorization dielectric optimized for NMOS and PMOS." This invention presents a method for forming a tensile SiN stress layer that enhances stress memorization in NMOS transistors without degrading PMOS transistors. The process involves a CMOS integrated circuit that is processed through a NMOS source and drain implant, while avoiding NMOS source and drain anneal. A SiN dielectric layer is deposited with specific characteristics, ensuring a high Si-H/N-H bond ratio and a tensile stress exceeding 150 MPa. The CMOS integrated circuit undergoes annealing after the deposition of the SiN dielectric layer, which is subsequently removed from parts of the integrated circuit.

Career Highlights

Kanan Garg is currently employed at Texas Instruments Corporation, where he applies his expertise in semiconductor technology. His work focuses on developing innovative solutions that improve the efficiency and performance of integrated circuits.

Collaborations

Kanan collaborates with talented colleagues, including Haowen Bu and Mahalingam Nandakumar, contributing to a dynamic and innovative work environment.

Conclusion

Kanan Garg's contributions to semiconductor technology, particularly through his patented methods, highlight his role as an influential inventor in the field. His work continues to impact the development of advanced electronic components.