Jyun-Kai Hu

Title: Innovations of Jyun-Kai Hu

Introduction

Jyun-Kai Hu is a notable inventor based in Tainan, Taiwan. He has made significant contributions to the field of low-density parity-check (LDPC) decoding. His innovative work focuses on improving hardware utilization in decoding architectures.

Latest Patents

Jyun-Kai Hu holds a patent for a "Layered decoding architecture with reduced number of hardware buffers for LDPC codes." This invention presents a layered decoding architecture that minimizes the number of hardware buffers required for LDPC decoding. The architecture achieves this by storing a variable-to-check message. When a check node initiates a new operation, a variable-to-check message (Q) is combined with a check-to-variable message (R) from a previous operation to update the APP value. The R value for the check node is then deducted from the APP value to derive a new variable-to-check message (Q). This message is stored in memory and integrated into the check node equation to produce a check-to-variable message. The resulting message is stored in a shift register, completing the update for both the check node and variable node. This innovative approach leads to improved hardware utilization and a reduction in the number of buffers, resulting in a smaller hardware area while maintaining convergence speed.

Career Highlights

Jyun-Kai Hu is affiliated with Tsinghua University, where he continues to advance research in his field. His work has garnered attention for its practical applications in enhancing decoding processes.

Collaborations

He has collaborated with notable colleagues, including Yeong-Luh Ueng and Hsueh-Chih Chou, contributing to various research initiatives.

Conclusion

Jyun-Kai Hu's innovative contributions to LDPC decoding architectures exemplify the impact of research on technology. His work not only enhances hardware efficiency but also paves the way for future advancements in the field.