Hsinchu, Taiwan

Jyh-Herny Wang

This inventor holds 1 USPTO granted patent. Top assignee: Faraday Technology Corporation. Active years: 2005.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jyh-Herny Wang. Retrieved from https://idiyas.com/inventor/jyh-herny-wang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 9(Granted Patents)


Company Filing History:


Years Active: 2005

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1 patent (USPTO):Explore Patents

Title: Innovations of Jyh-Herny Wang

Introduction

Jyh-Herny Wang is a notable inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of memory testing systems. His innovative work focuses on reducing peak power consumption in memory systems, which is crucial for enhancing the efficiency of electronic devices.

Latest Patents

Jyh-Herny Wang holds a patent for a "Memory test system for peak power reduction." This system includes a plurality of memories, memory built-in self-test circuits, and delay units. Each built-in self-test circuit features a controller that receives a clock signal and generates control signals to test the memories. The delay units are strategically placed between adjacent built-in self-test controllers to produce a delayed clock signal, optimizing the testing process.

Career Highlights

Wang is currently employed at Faraday Technology Corporation, where he continues to develop innovative solutions in memory technology. His work has been instrumental in advancing the capabilities of memory systems, making them more efficient and reliable.

Collaborations

Jyh-Herny Wang has collaborated with talented colleagues such as Cheng-I Huang and Chen-Teng Fan. Their combined expertise has contributed to the success of various projects within the company.

Conclusion

Jyh-Herny Wang's contributions to memory testing technology exemplify the importance of innovation in the electronics industry. His patent for a memory test system showcases his commitment to improving efficiency and performance in memory systems.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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