The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 20, 2005
Filed:
Oct. 08, 2002
Cheng-i Huang, Hsinchu, TW;
Chen-teng Fan, Hsinchu, TW;
Wang-jin Chen, Kaohsiung, TW;
Jyh-herny Wang, Hsinchu, TW;
Cheng-I Huang, Hsinchu, TW;
Chen-Teng Fan, Hsinchu, TW;
Wang-Jin Chen, Kaohsiung, TW;
Jyh-Herny Wang, Hsinchu, TW;
Faraday Technology Corp., Hsin-Chu, TW;
Abstract
A memory test system for peak power reduction. The memory test system includes a plurality of memories, a plurality of memory built-in self-test circuits and a plurality of delay units. Each of the memory built-in self-test circuits comprises a built-in self-test controller for receiving a clock signal and producing a plurality of required control signals to test one of the memories. Each of the delay units is coupled between two adjacent built-in self-test controllers. The clock signal input to one of the built-in self-test controllers is received by the delay unit to produce a delayed clock signal, and the delay unit outputs the delayed clock signal to the other.