Jung-Liang Chien

Title: Jung-Liang Chien: Innovator in Semiconductor Technology

Introduction

Jung-Liang Chien is a prominent inventor based in Sinying, Taiwan. He has made significant contributions to the field of semiconductor technology, particularly in improving the efficiency and reliability of semiconductor wafers. His innovative work has led to the development of a patented system that addresses critical challenges in wafer dicing operations.

Latest Patents

Jung-Liang Chien holds a patent for a "System and method for die to die stress improvement." This invention involves a semiconductor wafer that features a plurality of chip die areas arranged in an array. Each chip die area includes a seal ring area with one or more first sets of polygonal structures. The wafer also comprises scribe line areas between the chip die areas, which include one or more second sets of polygonal structures. The design ensures that the presence of proximate polygonal structures between the scribe line and seal ring areas balances stresses during the wafer dicing operation. This innovation is crucial for enhancing the performance and durability of semiconductor devices.

Career Highlights

Jung-Liang Chien is associated with Taiwan Semiconductor Manufacturing Company Limited, a leading player in the semiconductor industry. His work at this esteemed organization has allowed him to collaborate with other talented professionals and contribute to groundbreaking advancements in semiconductor technology.

Collaborations

Some of his notable coworkers include Chi-Cherng Jeng and Chih-Kang Chao. Their collaborative efforts have further propelled innovations within the semiconductor sector.

Conclusion

Jung-Liang Chien's contributions to semiconductor technology, particularly through his patented innovations, highlight his role as a key inventor in the industry. His work not only addresses existing challenges but also paves the way for future advancements in semiconductor manufacturing.